1. Field of the Invention
This invention is related to the field of digital systems and, more particularly, to low power mechanisms for managing displays in digital systems.
2. Description of the Relevant Art
As the power and complexity of computer systems increase, graphics operations are increasingly being performed using dedicated graphics rendering hardware. Accordingly, a graphics processing unit (GPU) may include various built-in and configurable structures within a display pipe for rendering images of pixel data to be presented via a display. These structures may implement various pipeline stages corresponding to, for example, rasterisation, overlaying, blending, clipping, dithering, color space conversion, frame rotation, frame buffering, etc.
In one embodiment, a video subsystem in a computing system may include multiple sources for video data. The design of a smartphone or computer tablet may include user interface layers, cameras, and video sources such as media players. Each of these sources may utilize video data stored in memory. A corresponding display controller may include multiple internal pixel-processing pipelines for these sources. Each memory request sent from the video subsystem includes both overhead processing and information retrieval processing. A large number of requests may create a bottleneck in the memory subsystem, and the repeated overhead processing may reduce the subsystem performance.
In order to minimize power consumption of the overall system, the system should attempt to enter a low-power mode whenever traffic is not being sent over the communication fabric to the memory controller. However, the memory subsystem may be unable to enter a low-power mode as one or more display pipelines continuously access the memory. The memory may be off-die synchronous dynamic random access memory (SDRAM) used to store frame data in frame buffers. The accesses of the SDRAM consume an appreciable amount of power in addition to preventing the memory subsystem from entering a low-power mode.
In view of the above, methods and mechanisms for minimizing the power consumption of a display pipeline are desired.